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Patent #US6985472B2
United States Patent
E05B49/00 • Electronic Door Locks & Secure Access Controllers
G07C9/00 • Access Gateways & Facility Entry Verification Systems
Encoder and decoder microchips suitable for use in remote control devices, are disclosed. The encoder microchip com- prises means for performing an encoding function on an identification number embedded in the said microchip and a combination of a unit number and a stepping counter value, so as to generate a transmission value which is only decod- able by a related decoding function having access to the same identification number. The decoder microchip com- prises means for decoding the transmission value into a decoded unit number and a decoded counter value and means for comparing the decoded counter value with a decoder counter value range. The encoder and decoder microchips are provided with means for changing, e.g. in a preferred mode incrementing, the counter values by a num- ber greater than one after a period of time, subsequent to the encoder microchip being activated or the decoder microchip receiving a transmission value. The encoder and decoder microchips are also provided with means for synchronizing the decoder microchip with a particular encoder microchip which has generated a synchronization command. 17 Claims, 7 Drawing Sheets /~ 26 28 — t+ SYNC MEMORY oy RX COUNTER 0 }~17 ~--»| RX COUNTER 1 1-18 CONTROL... --»}| RX COUNTER 2 }-19 >» RX COUNTER 3 }~-20 OUTPUTS {____» PUSH BUTTON 1}-21 ——_4 »|PUSH BUTTON 2}-22 bam ———— SYNC 23 OTHER 2d
Inventors & Locations
Frederick Bruwer
(Chandler, AZ US)
Patent #US6956495B2
United States Patent
G07C9/00 • Building Access Control Systems
G07C9/00174 • Smart Locks & Electronic Access Hardware
A control system for remotely activating an automatically opening door according to the present invention includes a plurality of transmitters held by different people and each transmitter transmits control signals. The system further includes a plurality of doors at least some of which are mounted in different buildings. Each of the doors includes an actuator for automatically opening and closing the door and a receiver electrically coupled to the actuator for receiving control signals from the transmitters and activating the actuator to open the door in response to the receipt of the control signals. In this system, any one of the transmitters may be used to open any of the doors. 11 Claims, 4 Drawing Sheets
Inventors & Locations
Christopher J. Klein
(Holland, MI US)
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Fanie Duvenhage
(Phoenix, AZ US)
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Kurt A. Dykema
(Holland, MI US)
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Mark S. Baynham
(Madison Heights, MI US)
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Microchip Technology Incorporated
(Chandler, AZ US)
•
Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 558 days. Appl. No.: , 857 Filed: May 22, 2001 Prior Publication Data US 2002/0175827 Al Nov. 28, 2002 Int. Cl.’ H04Q ; GO8C U.S. Cl. .19; .69; .72 Field of Search ............0.008 .19, 825.69, .72 References Cited U.S. PATENT DOCUMENTS 3, 824, 752 A * 4, 524 A * 5, 442, 340 A 5, 479
(155 A 12/1995 Zeinstra et A * 5/1996 Strab ... 5 A * 7/1996 Duhame et al. A 12/1996 Van Lente et al, SA 3/1997 Van Lente et al )
•
Thomas L. Welling
(Holland, MI US)
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oneLINK
(Holland, MI US)
Patent #US6937084B2
United States Patent
H02M1/00 • Digital Power Controllers & Inverter Modules
H02M1/38 • Motor Drive Controllers & Half-Bridge Gate Drivers
A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switch- ing devices that are connected to PWM hardware included in a processor. Complementary PWM output signals have dual deadtime delay in which the delay between the inacti- vation of the first signal and the activation of the second signal may be different than the delay between the inacti- vation of the second signal and the activation of the first signal. This provides an improved capability to deal with non-symmetric switching characteristics of the external switching devices, and the circuitry to which they are connected. The dual deadtime pulse width modulation gen- erator for a processor includes deadtime generation circuitry operable to generate a first pulse width modulated signal and a second pulse width modulated signal complementary to the first pulse width modulated signal, wherein there is a first delay between inactivation of the first pulse width modu- lated signal and activation of the second pulse width modu- lated signal, a second delay between inactivation of the second pulse width modulated signal and activation of the first pulse width modulated signal, and the first and second delays are not equal. The first delay and the second delay may be independently settable. 16 Claims, 6 Drawing Sheets
Inventors & Locations
Stephen A. Bowling
(Chandler, AZ )
Patent #US6847904B2
United States Patent
H03G3/00 • Programmable Gain Amplifiers (PGAs)
H03G3/001 • Digitally Controlled Analog Front-Ends (AFEs)
A programmable gain amplifier (PGA) controlled through a serial communications interface are fabricated on an inte- grated circuit (IC). A multiplexer (MUX) may also be included on the IC. The serial communications interface controls the gain of the PGA, MUX channel selection, and other functions of the PGA. Status of the PGA may also be obtained through the serial communications interface. By using a serial communications interface, the pin count of the PGAIC package may be kept to a minimum. 44 Claims, 2 Drawing Sheets Gain Setting Resistor Ladder Network ction MEMORY
Inventors & Locations
James B. Nolan
(Chandler, AZ US)
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Kumen E. Blake
(Gilbert, AZ US)
Patent #US6772090B2
United States Patent
G06F7/00 • Automotive Telematics & Secure Data Loggers
G06F7/38 • Automotive Instrument Clusters & Odometers
An improved vehicle odometer is provided with an encoder and a microcontroller. The encoder has a unique key that configures an encryption algorithm. The encryption algo- rithm can be in the form of circuitry or software or any combination there between. The encoder receives a incre- ment signal from the vehicle indicating that the vehicle has traveled a pre-determined distance. The encoder then incre- ments the odometer-related value and then encrypts it with the encryption algorithm. The encoder then wraps the encrypted odometer-related value into a data packet with a serial number. Only a suitably equipped computing device, such as a microcontroller, identify and correctly decrypt and process the encrypted odometer-related value, thereby pre- venting the tampering of the vehicle’s odometer. 11 Claims, 9 Drawing Sheets dentify Device by 314 erial Number or by a Function of the Serial Number Discard Data and Publish Error Message Decrypt Encrypted dometer Value and ‘ransmit to Display Device
Inventors & Locations
Brendon Hutton
(Erding, DE)
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Fanie Duvenhage
(Phoenix, AZ US)
Patent #US6728856B2
United States Patent
G06F9/00 • Microcontrollers & SoCs
G06F9/06 • Microcontrollers & SoCs
A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advan- tages of simultaneous program instruction and data access, yet provides a means to access program memory resident data without special purpose instructions. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory s; The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space. 13 Claims, 4 Drawing Sheets 100 “PROCESSOR £105 “PROG. MEMORY | cite | Es FETCH OECODE Fits | iNsTRUGTION EXECUTION UNITS ~~ WREGISTERS. DATA MEMORY (XANDIOR ¥) AND W REGISTERS 15 PHERALS
Inventors & Locations
James H. Grosbach
(Scottsdale, AZ US)
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Joshua M. Conner
(Apache Junction, AZ US)
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Michael Catherwood
(Pepperell, MA US)
Patent #US6708268B1
a2) United States Patent
G06F9/00 • Microcontrollers & SoCs
G06F9/06 • Microcontrollers & SoCs
A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register, Thus increasing performance and decreasing program memory usage. 142 Claims, 95 Drawing Sheets 12 Address <12> 108 a Program Memory, (up to 2M Bytes) Address Latch
Inventors & Locations
Edward Brian Boles
(Mesa, AZ US)
Patent #US6700931B1
United States Patent
H04L25/00 • RFID Transceivers & Baseband Processors
H04L25/38 • RFID Tags & Synchronous Communication Modules
Aradio frequency identification (RFID) tag device having a pulse position modulation (PPM) decoder circuit which calculates a relative frequency relationship between an inter- nal clock-oscillator of the RFID tag device and an external PPM source such as a RFID tag reader, and then synchro- nizes the RFID tag device PPM decoder circuit to the required precision for reliable PPM symbol decoding. The PPM decoder is synchronized by measuring the “counts per pulse” (CPP) from a calibration cycle having a plurality of pulses in a single symbol frame. 23 Claims, 5 Drawing Sheets 128 CLK 226d Q& Modulo 16 Q, Counter Q, Q 226c To Symbol 226b Register 130 226 (Modulo-16 Pulse Position) Set at rising edge of last calibration symbol pulse
Inventors & Locations
Lee Furey
(Phoenix, AZ US)
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Ron Salesky
(Tabernacle, NJ US)
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Sam Alexander
(Phoenix, AZ US)
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Shinichiro Inui
(Haddonfield, NJ US)
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William F. Gallagher
(Phoenixville, PA US)
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Youbok Lee
(Chandler, AZ US)
Patent #US6687293B1
United States Patent
G06K19/00 • RFID Tags & Smart Labels
G06K19/06 • RFID Transponder ICs
Aradio frequency identification (RFID) tag device having a pulse position modulation (PPM) decoder circuit which calculates a relative frequency relationship between an inter- nal oscillator of the RFID tag device and an external PPM source such as a RFID tag reader. The PPM decoder circuit is calibrated to the difference between the external PPM frequency source (i.e, RFID tag reader) and the internal clock-oscillator of the RFID tag device, which is performed in a single measurement during one calibration symbol period. 11 Claims, 8 Drawing Sheets 116 BIT To N_ be} winpow f+] SYNEOE L+ SYMBOL R| | COUNTER DATA 118 128 130
Inventors & Locations
Samuel Alexander
(Phoenix, AZ US)
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Stephen R. Loyer
(Gilbert, AZ US)
Patent #US6556046B1
United States Patent
G06F13/00 • Motherboards, System-on-Chips, and Bus Interfaces
G06F13/38 • Input/Output Controllers & Interface Cards
The present invention relates generally to functional path- way configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More pai larly, the present invention relates generally to the functional pathway configuration at the interface between a digital device and a radio frequency device (wireless RF digital device), and the circuitry of a system including the packaged devices. Even more particularly, the present invention relates to a wireless radio frequency digital device functional pathway configuration for the interface between the wireless radio frequency digital device and a system in which the wireless radio frequency digital device is embedded. 19 Claims, 2 Drawing Sheets Vop +(])1 20100< Vss GPSIOSCI/CLKIN <> ( PS/DATAASK —> (J VoorF + (C4 ANT2 + 2 GP4/OSC2 «+ C] 3 18 [<> GP1 GP3/~MCLR/Vep —(] 4 47(1 «+ GP2/TOCKI XTAL + {) 5 16{]— FSKouT RFENIN + (6 15[)<— DATAFSK CLKOUT «(] 7 1400 <> LF 8 9 41— ANT1 o
Inventors & Locations
Farron L. Dacus
(Chandler, AZ US)
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Johannes A. Van Niekerk
(Tempe, AZ US)
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Richard J. Fisher
(Glendale, AZ US)
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Roger D. St. Amand
(Tempe, AZ US)
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Steven R. Bible
(Chandler, AZ US)
Patent #US6552625B2
United States Patent
H02P27/00 • Industrial Motor Drives & Controllers
H02P27/04 • Inverter-Driven Motor Controllers
A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a proces- sor. A pulse width modulation generator for a processor includes fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry oper- able to drive the pulse width modulation output to a defined state associated with the selected fault input. 16 Claims, 3 Drawing Sheets 208A I rate
Inventors & Locations
Stephen A. Bowling
(Chandler, AZ US)
Patent #US6509825B1
United States Patent
H04B1/00 • Wireless Communication Integrated Circuits
H04B1/59 • RFID Tags & Wireless Transponder Chips
Aradio frequency transponder device in an integrated circuit package requires only one dedicated pin for connection to a parallel resonant tuned circuit for receiving a remote signal. The one dedicated pin has a capacitor which blocks direct current (DC) flow and allows independent DC biasing of a radio frequency amplifier for increased signal amplification gain. Another package pin used for common power or ground connections supplies the second connection to the resonant tuned circuit. Multiple transponder inputs may be implemented in a single integrated circuit package using only one dedicated pin per input plus one common pin which may be used for another purpose, such as a power or a ground connection. 21 Claims, 6 Drawing Sheets DC Bias Level Measurement & Control
Inventors & Locations
Pieter Schieke
(Phoenix, AZ US)
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Willem J. Marneweck
(Tempe, AZ US)
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Willem Smit
(Chandler, AZ US)
Patent #US6480110B2
a2) United States Patent
H01Q1/00 • Antenna Hardware & Components
H01Q1/12 • Antenna Mounting Hardware
67)
Inventors & Locations
Lee
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Youbok Lee
(Chandler, AZ US)
Patent #US6459335B1
United States Patent
H03M1/00 • Data Converters & Microcontrollers
H03M1/10 • Data Converters & Microcontrollers
An auto-calibration circuit minimizes input offset voltage in an integrated circuit analog input device. The auto- calibration circuit may also calibrate a plurality of analog input devices on an integrated circuit die or in a multi-chip package (MCP). The auto-calibration circuit and analog input device(s) may be fabricated in combination with a microcontroller system on an integrated circuit die or in an MCP. The auto-calibration circuit controls input offset volt- age compensation circuit that counteracts or compensates for input offset voltage so as to minimize voltage error at the output of the analog input device. A digital control circuit applies a digital word to the input offset voltage compen- sation circuit for generating the required input offset voltage compensation. A linear search or binary search of various values of the digital word may be used by the digital control circuit. The digital control circuit switches the inputs, the output and feedback-gain determining resistors for the ana- log input device during a calibration mode. A voltage comparator compares the output of the analog input device and a voltage reference. When the output of the analog input device is equal to or greater than the voltage reference, the comparator output signals the digital control circuit by changing its output logic level. The input offset voltage compensation circuit of the analog input device has a storage register or memory that retains the digital word which compensates for the input offset voltage. 33 Claims, 4 Drawing Sheets » Amp fset trim Digital Control ‘. 200
Inventors & Locations
Hartono Darmawaskita, Chandler; Layton Eagar, Mesa; Miguel Moreno
(Gilbert, all of AZ US)
Patent #US6456044B1
United States Patent
H02J7/00 • Battery Charger ICs & Power Management ICs (PMICs)
H02J7/90 • Switch-Mode Battery Charger Controllers
Asingle integrated circuit package for controlling the charg- ing circuits of a battery charger. The single integrated circuit package comprises a microcontroller, switch mode power supply controller(s), analog to digital converter and analog input multiplexer which may be fabricated on a single integrated circuit dic, or the microcontroller may be on one integrated circuit die, and the remaining aforementioned circuits may be on a second integrated circuit die. The switch mode power supply controller is adapted for connection to a power converter which is used to control the voltage and/or current to a battery being charged. The power converter may also be on the same integrated circuit die as the switch mode power supply controller, or may be on a separate semicon- ductor die but included in the single integrated circuit package. Single or multiple batteries may be charged using charging algorithms specifically tailored to each battery. Batteries being charged may have a different capacity, voltage, or chemistry type. State of charge and time to reach a fully charged condition for each battery may also be different. 29 Claims, 7 Drawing Sheets —~112 BATTERY ——~118 one Ye 4 - 108 - | 1 fO DIGITAL] ANALOG INPUT ERTER MULTIPLEXER | NTROLLER ! t A ee eee 100
Inventors & Locations
Hartono Darmawaskita
(Chandler, AZ US)
Patent #US6424211B1
United States Patent
H03F3/00 • Operational Amplifiers & Linear ICs
H03F3/45 • Operational Amplifiers & Linear ICs
An operational amplifier is trimmed electrically using non- volatile fuses. The non-volatile fuses may be programmed electrically without destroying any passivation layers or other devices on the electronic component. In the case of an integrated circuit analog component, the ttimming may be performed either at the wafer level or at the packaging level. The trimming may be performed specifically to adjust the quiescent current or offset voltage of the operational ampli- fier. 26 Claims, 9 Drawing Sheets f_ 289 7— 960 FUSE IN NPGM
Inventors & Locations
James B. Nolan, Chandler; Bonnie Baker
(Tucson, both of AZ US)
Patent #US6349058B1
a2) United States Patent
G11C7/00 • Memory Integrated Circuits
G11C7/10 • Memory Controller Components
An electronic circuit includes a non-volatile memory that has several memory cells. The output of the non-volatile memory is connected to the inputs of several latches. Each latch has an output adapted to be read independently. A refresh circuit is connected to address lines of the non- volatile memory and to the write pins of cach of the latches. The data contained in the memory cells of the non-volatile memory is represented by the data contained in the latches. 22 Claims, 3 Drawing Sheets
Inventors & Locations
Joseph A. Thomsen
(Gilbert, AZ US)
Patent #US6345353B2
United States Patent
G06F7/00 • Microprocessors & Central Processing Units
G06F7/76 • Processor Core Components
The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding loca- tion to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execu- tion of a current instruction. 8 Claims, 1 Drawing Sheet AVE MASTER (CH LATCH INCREMENT) DECREMENT 5 ' 1 ' ' i ' t : 24 201 ! ' ' ' i ' I { | ' { ' { { { | : cN4 STACK RAM 16
Inventors & Locations
Stephen Allen, Chandler; Igor Wojewoda
(Phoenix, both of AZ US)
Patent #US6339413B1
United States Patent
G06F1/00 • Microcontrollers & SoCs
G06F1/26 • Ultra-Low-Power Microcontrollers
A device including a microcontroller fabricated on a semi- conductor chip is used to control an LCD display of an external system intended to be controlled by the microcon- troller. The microcontroller enters a sleep state in which it operates in a battery power conservation mode during peri- ods of time when functional activity of the microcontroller is reduced. The microcontroller awakens from the sleep state for resumption of activity when such a period ends. Timing to the LCD is decoupled from the microcontroller’s own internal clock when the independent internal on-chip clock, which may be an RC oscillator, is selected by the user of the device. This allows the chip to continue to drive the LCD display even though the microcontroller’s internal clock has stopped during the sleep. 6 Claims, 11 Drawing Sheets ILTAGES 13 DIGITAL TESTER
Inventors & Locations
Rodney Drake, Phoenix; Brian Boles
(Mesa, both of AZ US)
Patent #US6321319B2
United States Patent
G06F15/00 • Microprocessors & Central Processing Units
G06F15/16 • Multi-Processor Systems
A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized pro- gram memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction. 13 Claims, 1 Drawing Sheet 10 ) 4 | ADDRESS pROGRAM BUS MEMORY _QUTPUT : | Lo |
Inventors & Locations
Rodney J. Drake; Randy L. Yach; Joseph W. Triece, all of Phoenix; Jennifer Chiao, Chandler; Igor Wojewoda, Phoenix; Steve Allen
(Chandler, all of AZ US)
Patent #US6225678B1
a2) United States Patent
H10D84/00 • Monolithic Integrated Circuits
H10D84/201 • Passive Component Integration
A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control para nd fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell. 6 Claims, 7 Drawing Sheets
Inventors & Locations
Randy L. Yach, Phoenix; Igor Wojewoda
(Tempe, both of AZ US)
Patent #US6204708B1
United States Patent
H03K3/00 • Integrated Circuits & Digital Logic
H03K3/02 • Clock Generators & Timing ICs
An improved master-slave flip-flop that is characterized by anovel clock generator. The improved flip-flop preserves the true mast ave relationship by ensuring a two ste ing process is executed by non-overlapping cl clock generator features an inverter in combin current limiter. The current limiter has the effect of shifting the trip point of the inverter such that non-overlapping clocks may be derived from a single master clock signal or a master clock signal and its complement. 18 Claims, 9 Drawing Sheets s” I -102 40 CLK SLAVE Q LATCH -103
Inventors & Locations
Sam E. Alexander
(Phoenix, AZ US)
Patent #US6180433B1
a2) United States Patent
H10W90/00 • Integrated Circuit Packages
H10W90/811 • System-in-Package (SiP) Modules
A combination inductive coil and integrated circuit semi- conductor chip is provided in a single lead frame package. The lead frame is preferably made of a copper alloy and has a flat configuration. The chip is electrically connected to end portions of the inductive coil thus permitting the inductive coil to function as an antenna for the chip. 20 Claims, 2 Drawing Sheets 12 14 LI a a DS 20
Inventors & Locations
Lee Furey, Phoenix; Joseph Fernandez
(Gilbert, both of AZ US)
Patent #US6166960A
United States Patent 115
G11C16/00 • EEPROM & Flash Memory Integrated Circuits
G11C16/02 • EEPROM Memory Chips
An electronic system, comprising a digital processor and an EEPROM, has circuit logic and program software or firm- ware for determining if a programming voltage level is sufficient for reliably programming the EEPROM. A charge pump is enabled and generates a voltage used for program- ming of the EEPROM. The enabled charge pump thereby loads a battery power supply. In addition, a test load may be connected to the output of the charge pump to simulate the EEPROM load during a programming operation to the EEPROM. The charge pump output voltage is measured to determine if at least a desired voltage value is obtained. Once the charge pump voltage level has been pre-qualified for the desired voltage value, an actual programming opera- tion to the EEPROM may be performed. If the voltage level does not reach the desired value then a programming opera- tion is inhibited and the electronic system may alarm or shut down operation. The charge pump voltage level is a good indication and measure of battery charge condition under actual EEPROM programming load conditions.
Inventors & Locations
Willem J. Marneweck, Tempe; Willem Smit, Chandler; Meiling Chen
(Tempe, all of Ariz )
Patent #US6166650A
United States Patent 115
H04Q9/00 • Wireless Remote Controls & Transmitters
G07C9/00 • Access Control Terminals & Security Gates
A method and system for the remote control of devices having a secure self learn capability. The system includes an encoder and a decoder, the encoder encoding variable infor- mation including a user key using a non-linear algorithm to produce an encoded value transmitted to the decoder, the decoder decoding the value using the same algorithm. In a learning mode a new encoder is to be added to the system. The new encoder produces an encoded value using a key generation seed. The decoder, upon receiving the encoded key generation seed, produces a decoding key based upon the decoded key generation seed. The decoding key is stored in the decoder memory allowing valid recognition of the new encoder in a secure manner.
Inventors & Locations
Frederick Bruwer
(Chandler, Ariz )
Patent #US6151238A
United States Patent 115
G06F11/00 • Microcontrollers & SoCs
H10W46/00 • Integrated Circuits
An integrated circuit having a microcontroller, mask pro- grammed read only memory, functions such as clock oscillator, analog-to-digital converter, timers, etc., where each may be adjusted with a digital input to a desired calibration value. The digital input resulting in the desired calibration value being stored in a programmable fuse array.
Inventors & Locations
Willem Smit, Chandler; Paul Hofhine, Mesa; Clark Rogers
(Phoenix, all of Ariz )
Patent #US6122205A
United States Patent 115
G11C8/00 • Memory Integrated Circuits
G11C8/08 • Memory Controllers & SoCs
A system for reading a memory cell of a memory array at voltage levels lower than an erased threshold voltage of the memory array. The system uses a voltage regulator which is coupled to the memory array for charging a desired row of the memory array to a supply voltage. The voltage regulator is further used for clamping the desired row at a voltage level which is no higher than a maximum programmed threshold voltage of the memory array. The voltage regulator is able to perform these functions while consuming no DC current. A voltage booster is coupled to the voltage regulator and to the memory array. The voltage booster is used for raising the voltage level of the desired row to a voltage above the maximum erased threshold voltage of the memory cell. This allows the memory cell to be read at voltage levels which are lower than the threshold voltage of the memory array.
Inventors & Locations
Randy L. Yach
(Phoenix, Ariz )
Patent #US6103576A
United States Patent 115
H10D30/00 • Discrete Transistors & Integrated Circuit Logic
H10D30/60 • MOSFET & CMOS Integrated Circuits
A merged two-tra:
Inventors & Locations
Neil Deustcher, Tempe; Jack Wong
(Phoenix, both of Ariz )
Patent #US6098160A
United States Patent 115
G06F12/00 • Processor Core Subsystems
G06F12/02 • Microcontroller Memory Units
A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode, An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
Inventors & Locations
Rodney J. Drake; Randy L. Yach; Igor Wojewoda; Joseph W. Triece, all of Phoenix; Brian Boles, Mesa; Darrel Johansen
(Tempe, all of Ariz )
Patent #US6091935A
United States Patent 115
G06K19/00 • Smart Cards & RFID Tags
G06K19/06 • Smart Cards & RFID Tags
An improved integrated circuit transponder device is pre- sented comprising, in combination, a single, externally wireless package enclosing an integrated circuit semicon- ductor chip, a coil within the package being selectively exposed to an electromagnetic field, and a detection portion on the integrated circuit semiconductor chip and being coupled to each end of the coil for detecting when voltages at each end of the coil are approximately equal over a period of time. The detection portion includes an exclusive NOR gate coupled to each end of the coil for determining when the coil voltages are equal, and the output of the exclusive NOR gate is input to a filter before being delivered to the remainder of the device circuitry.
Inventors & Locations
Sam Alexander; Lee Furey
(both of Phoenix, Ariz )
Patent #US6078208A
United States Patent 115
G01K7/00 • Temperature Sensors & Thermal Management ICs
G01K7/01 • Silicon Temperature Sensors & Thermal Diodes
A precision temperature sensor produces a clock frequency which varies predictably over wide variations of ambient temperature. The invention has a oscillation generator, two independent current generators, a reference oscillator and a frequency counter. The outputs of the two independent current generators are combined to provide an approxi- mately linear capacitor charging current which is directly proportional to changes in temperature. The capacitor charg- ing current is used to drive the oscillation generator which outputs a clock frequency that is approximately linearly dependent on temperature with determinable slope and intercept. The frequency counter compares the output of the oscillation generator with the independent reference oscil- lator to compute a digital value for temperature. The preci- sion temperature sensor is implemented on a single, mono- lithic integrated circuit.
Inventors & Locations
James B. Nolan; Hartono Darmawaskita
(both of Chandler, Ariz )
Patent #US6060955A
United States Patent 115
H03K3/00 • Clock Generators & Oscillators
H03K3/01 • Clock Generators & Oscillators
A voltage compensated oscillator circuit having a resistor capacitor (RC) circuit for setting a frequency of oscillation for the oscillator circuit. A switching circuit with hysterisis is coupled to the RC circuit for providing upper and lower threshold limits. The upper and lower threshold limits being used for controlling the direction of switching of the oscil- lator circuit. By adjusting the upper and lower threshold limits, one may compensate for voltage signal fluctuations so that the frequency of oscillation will not change due to power supply voltage fluctuations.
Inventors & Locations
Joseph A. Thomsen
(Gilbert, Ariz. [73] )
Patent #US6057721A
United States Patent 115
H03K17/00 • Power Management & Control ICs
H03K17/22 • Integrated Circuit Subsystems & Power Management
A fast start-up circuit for use in integrated circuits where there are internal nodes of reference circuits that need to be charged to a predetermined voltage level at a quicker rate than that delivered by the typical ramping up of supply power. The circuit a current driven approach, which is unique from the voltage driven approaches found in the prior art. The circuit is comprised of a high gain reference circuit and a current generator. The reference circuit is comprised of a bias generator and a high gain amplifier. The invention is characterized by a current generator which is capable of rapidly injecting relatively high levels of current into the reference circuit or sinking relatively high levels of current from the reference circuit or both. The invention is further characterized by a current driven feedback loop which deactivates the current generator once start-up is achieved and the high gain reference circuit approaches the quiescent point.
Inventors & Locations
James B. Nolan, Chandler; David Susak
(Phoenix, both of Ariz )
Patent #US6057705A
United States Patent 115
H03K19/00 • Programmable Logic Devices & Microcontrollers
H03K19/0175 • Semiconductor Interface ICs
The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of addr or as alternate I/O pins. The object of the invention i provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programming logic, configura- tion logic, selection logic and a set of pins that may be configured as per the programmer’s requirements. The invention is to exist on a single, monolithic semiconductor device,
Inventors & Locations
Igor Wojewoda; Rodney J. Drake
Patent #US6055211A
United States Patent 115
G06F12/00 • Microcontrollers & SoCs
G06F12/02 • Microcontrollers & SoCs
A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on page 0 of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables which are located on page 0 of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in the op-code instruction currently being executed by the micro- controller.
Inventors & Locations
Randy L. Yach
(Phoenix, Ariz )
Patent #US6052035A
United States Patent 115
H03K3/00 • Integrated Oscillators & Real-Time Clocks
H03K3/02 • Precision Clock Generators
An oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator, two independent current generators, a transition detector and a clock inhibitor. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current that is independent of tempera- ture. The oscillator is capable of three modes of operation: fast mode, slow/low power mode and sleep mode, which are controlled by the transition detector in response to external control signals. When the transition detector transitions from one mode to another, it controls the clock inhibitor to block aclock output of the oscillator generator for a predetermined number of clock cycles to allow the clock output to stabilize. The oscillator is implemented on a single, monolithic inte- grated circuit.
Inventors & Locations
James B. Nolan, Chandler; Ryan Scott Ellison, Mesa; Michael S. Pyska
(Phoenix, all of Ariz )
Patent #US6049289A
United States Patent 115
G07C9/00 • Physical Access Control Systems
G07C9/00174 • Electronic Locks & Keyless Entry Systems
A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code “grabbing”. The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system auto- matically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry. A multibit hopping code is transmitted from each transmitter to the receiver with each transmitter operation in the operate mode of the system and the hopping code changes with cach transmission to prevent theft or code grabbing and resultant unauthorized operation of the system.
Inventors & Locations
Dennis W. Waggamon, North Canton, Ohio; Willem J. Marneweck, Tempe, Ariz.; Vivien N. Delport, Phoenix, Ariz.; Frederick J. Bruwer
(Chandler, Ariz )
Patent #US6047380A
United States Patent 115
G06F13/00 • Microcontrollers & SoCs
G06F13/10 • Control Units & Interface Modules
A semiconductor device for receiving analog input signals includes a microprocessor for processing signal information. The microprocessor is put in a sleep mode when not called upon to process signal information, and is either left in that mode or awakened depending on the level of a continuously variable analog input signal relative to a programmed threshold level. If the relative levels of the analog input signal and the programmed threshold level result in the microprocessor being awakened, information contained in the analog input signal is processed to initiate a selected action. In typical applications, the semiconductor device performs a control function, such as to control the operation of an external circuit in response to information from at least one continuously variable analog input signal derived from the external circuit. The microprocessor, when awakened, assists in controlling the external circuit to restore that analog input signal to a predetermined level distinct from the threshold level. In some applications, such as for battery charging and monitoring, the device is responsive to a plurality of different continuously variable analog input signals derived from the external circuit and indicative of a specified circuit function thereof, These signals are applied to the device in interleaved sequence according to a priority that depends on their respective rates of variation. The specified circuit function of the external circuit such as the
Inventors & Locations
James Nolan, Chandler, Ariz.; Brian Dellacroce
(Colorado Springs, Colo )
Patent #US6029241A
United States Patent 115
G06F12/00 • Microprocessors & Memory Controllers
G06F12/02 • Microprocessors & Memory Controllers
A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor archi- tecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode. An instruction register is coupled to the selection circuit for supplying a bank address values for an instruction to be executed in a direct long addressing mode and for supplying a register address within a bank for the instruction to be executed in a direct short addressing mode.
Inventors & Locations
Igor Wojewoda, Phoenix; Sumit Mitra, Tempe; Rodney J. Drake
(Phoenix, all of Ariz )
Patent #US6020792A
United States Patent 115
H03B5/00 • Clock Generators & Oscillators
H03B5/20 • RC Relaxation Oscillators
A precision relaxation oscillator with temperature compen- sation produces a stable clock frequency over wide varia- tions of ambient temperature. The invention has a oscillation generator and two independent current generators. The out- puts of the two programmable, independent current genera- tors are combined to provide a capacitor charging current
Inventors & Locations
James B. Nolan; Hartono Darmawaskita, both of Chandler; R. Scott Ellison; David Susak
(both of Phoenix, all of Ariz )
Patent #US6016019A
United States Patent 115
H03M1/00 • Data Converters (ADCs and DACs)
H03M1/12 • Analog-to-Digital Converters (ADCs)
A capacitor array layout technique for improving capacitor array matching. A capacitor array is laid out in a geometrical configuration wherein the geometrical configuration has a centerpoint. The geometrical configuration is divided into a plurality of first sections wherein each of the plurality of first sections have a corresponding second section diagonally located from and at an approximately equal distance from the centerpoint as said first section. Each of the of second sections house a capacitor set of a predetermined value wherein each of the plurality of first sections house a capacitor set of an equal value as the corresponding second section.
Inventors & Locations
Igor Wojewoda
(Tempe, Ariz )
Patent #US5998980A
United States Patent 115
H02M7/00 • Power Supplies & Energy Converters
H02M7/02 • AC-DC Power Rectifiers
The highly efficient multi-frequency voltage regulating cir- cuit is capable of converting magnetic field energy to electrical energy for charging either a battery or an energy storage device such as a capacitor. The invention provides a magnetic field sensor circuit that measures the strength of incoming magnetic field energy with respect to a reference current. The invention also provides for a programmable magnetic field detection circuit which is used to adjust the detection level of the inductor-capacitor magnetic field converter circuit. A discharge expediter circuit is provided to improve the efficiency of the magnetic field converter circuit by discharging excess energy.
Inventors & Locations
Pieter Schieke, Phoenix; Willem Smit
(Chandler, both of Ariz )
Patent #US5991196A
United States Patent 115
G11C16/00 • Flash Memory Devices
G11C8/00 • Memory Controllers & SoCs
An improved reprogrammable memory device permits defi- nition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.
Inventors & Locations
Joseph A. Thomsen; Timothy J. Phoenix, both of Gilbert; Brian Boles, Mesa; Henry Pena, Chandler; Gordon E. Luke
(Mesa, all of Ariz )
Patent #US5987583A
United States Patent 115
G06F9/00 • Microprocessors & Central Processing Units (CPUs)
G06F9/06 • Microcontrollers & Embedded Processors
A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addr through use of virtual register address instruction set having a plurality of instructions. instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.
Inventors & Locations
Joseph W. Triece, Phoenix; Sumit K. Mitra
(Tempe, both of Ariz )
Patent #US5974475A
United States Patent 115
H04L12/00 • Network Switches & Communication Busses
H04L12/66 • Communication Bridges & Gateways
Amethod for allowing flexible multiple access to a serial bus by a plurality of circuit boards. Before a circuit board can be used on a common serial bus with other circuit boards, a unique software address must be assigned to each circuit board. The unique software address is assigned by having a bus master device issue Assign Address commands which utilizes a unique serial number which is stored on each circuit board. The Assign Address command queries each of the circuit boards coupled to the serial bus and assigns a unique software address to each circuit board that fully responds, The Assign Address command is repeated for each circuit board on the serial bus until all of the circuit boards on the serial bus have been assigned a unique software address.
Inventors & Locations
John Day, Marlboro, Mass.; Nathan John, Chandler, Ariz.; Bruce Negley, Phoenix, Ariz.; Shannon Poulin
(Tempe, Ariz )
Patent #US5958039A
United States Patent 115
G06F7/00 • Central Processing Units & Processors
G06F7/76 • Processor Logic Components
The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding loca- tion to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will the next unutilized location in the stack memory de for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execu- tion of a current instruction.
Inventors & Locations
Stephen Allen, Chandler; Igor Wojewoda
(Phoenix, both of Ariz )
Patent #US5956589A
United States Patent 115
H10W10/00 • Integrated Circuits & Microprocessors
H10W10/01 • Semiconductor Fabrication Equipment & Materials
A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate
Inventors & Locations
Roger D. St. Amand; Neil F. Deutscher, both of Temple; Robert P. Ma
(Phoenix, all of Ariz )
Patent #US5899570A
United States Patent 115
G01K7/00 • Digital Temperature Sensors & Measurement ICs
G01K7/16 • Resistive Temperature Sensors
A time-based digital temperature sensing system has a first oscillator which is temperature sensitive. The first oscillator has a temperature coefficient which allows the first oscillator to generate an output signal which varies linearly as a function of temperature. A second oscillator is provided and is used to generates a reference clock signal. The outputs from the first and the second oscillator are coupled to a timer. The timer has a clock input coupled to an output of the second oscillator and an enable input coupled to an output of the first oscillator. From these input signals, the timer generates a number indicative of a length of time the timer is enabled by the first oscillator. The number is proportional to a current temperature of a material that is being monitored by the temperature sensing system.
Inventors & Locations
Hartono Darmawaskita; James B. Nolan
(both of Chandler, Ariz )
Patent #US5889829A
United States Patent 115
H03L7/00 • Phase-Locked Loop (PLL) Integrated Circuits
H03L7/06 • Phase-Locked Loop (PLL) Integrated Circuits
A phase-locked loop (PLL) circuit is used to synchronize a local clock frequency with an edge of a reference clock frequency, employing a phase detector to compare the local clock frequency and the reference clock frequency to gen- erate a control signal indicative of the need to increase or to decrease the local clock frequency for phase locking thereof to the reference clock frequency. A voltage controlled oscil- lator (VCO) is responsive to a signal voltage derived from the control signal to vary the local clock frequency as necessary to achieve phase locking. A loop filter has a reference voltage threshold level which is pre- programmable to enable the loop filter to respond to the control signal by adjusting the signal voltage as a virtual step function toward the programmed reference voltage thresh- old level before application to the VCO, and then cycling up and down in a search for a stable control signal voltage to reduce the time necessary to achieve the desired phase locking.
Inventors & Locations
Jennifer Yuan Chiao, Chandler; Randy L. Yach
(Phoenix, both of Ariz )
Patent #US5874931A
United States Patent 115
G09G3/00 • LCD Controller Integrated Circuits
G09G3/20 • Dot-Matrix LCD Controllers
A single semiconductor chip device is utilized for control- ling an external system which has a liquid crystal display (LCD) associated therewith. A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches and a single slave data storage latch shared by all of the plurality of master storage latches. A microcontroller has a central processing unit (CPU) for communicating with the master storage latches via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch with data from each of the master storage latches and downloads the updated data from the single slave storage latch to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch. Consequently, data in cach master storage latch may be changed periodically by the CPU without interference with downloading of updated data from the single slave storage unit.
Inventors & Locations
Rodney Drake, Phoenix; Ray Allen
(Payson, both of Ariz )
Patent #US5874863A
United States Patent 115
H03L7/00 • Clock Generation & Timing ICs
H03L7/06 • Frequency Synthesizers & Clock Generators
A phase-locked loop (PLL) circuit has a phase comparator for comparing the phases of a local clock frequency and a reference frequency to generate a control signal indicative of a direction of adjustment of the local clock frequency for reducing the phase difference between the two frequencies. A voltage controlled oscillator (VCO) of the PLL responds to application of a control voltage thereto to generate an oscillation signal frequency from which the local clock frequency is derived. A loop filter responds to the control signal from the phase comparator to develop a control voltage for application to the VCO to adjust the local clock frequency in the direction indicated by the control signal to reduce the relative phase difference. The loop filter has a start-up cil reference frequency after a predetermined number of cycles following commencement of operation or reset of the PLL circuit as being indicative of stabilization of the reference frequency, and is responsive to detection of such selected edge for promptly producing a linear boost of the control voltage from an initial level of substantially zero volts to a predetermined pull-up level exceeding the level of control voltage required to achieve phase locking. This reduces the time interval required to achieve phase locking, measured from the selected cycle edge. The loop filter is also respon- sive to the control voltage reaching the pull-up level to incrementally reduce the control voltage to the level required to achieve phase locking.
Inventors & Locations
Igor Wojewoda, Phoenix; Jennifer Yuan Chiao
(Chandler, both of Ariz )
Patent #US5870409A
United States Patent 115
G09G3/00 • LCD Display Modules & Controllers
G09G3/006 • Automated Test Equipment & Display Drivers
A method is disclosed for testing a high speed microcon- troller fabricated on a semiconductor chip, and for testing relatively low speed functions of a liquid crystal display (LCD) module on the chip that drives an off-chip LCD for an external system to be controlled by the microcontroller with a plurality of discrete analog voltage levels for per- forming the LCD functions. Digital values are multiplexed in time slots of a test waveform to simulate in high speed digital format of a test mode the low speed timing, relative magnitude and functionality of analog voltage levels used to drive the LCD; A high speed driver is selectively coupled to a pin of the chip, to which the discrete analog voltage levels are normally applied at low speed to drive the LCD, and the test waveform is applied to the high speed driver. The digital values and timing that appear on the pin are then monitored as an indication of proper functionality of the LCD module. The high speed driver is switched out and the normal low speed LCD driver is switched back for return to an LCD user mode when the test mode is completed. Monitoring the pin with a digital tester allows verification that pin pulses in predetermined time slots indicate the corresponding analog voltage level is being applied at the proper time during normal operation of the LCD module, and digitally testing of continuity in an analog channel. A transistor normally employed on the chip for electrostatic discharge protection is activated to selectively couple the high speed driver to the pin for the high speed testing mode.
Inventors & Locations
Randy Yach, Phoenix, Ariz.; Rodney Drake
(Phoenix, Ariz )
Patent #US5861861A
United States Patent 115
H02M3/00 • DC-DC Power Converters & Regulators
H02M3/02 • DC-DC Power Converters
Apparatus for providing multiple of discrete voltage levels to drive a liquid crystal display (LCD) from an LCD module on board a microcontroller chip includes a charge pump with a switched-capacitor that develops the discrete voltages as multiples of the value of a base voltage that remains sub- stantially without change irrespective of change in the supply voltage. A switched-capacitor charging circuit selec- tively charges a capacitor to produce successive additive charges individually retrievable from the capacitor. An LCD drive selectively transmits the discrete voltage levels to activate the LCD according to status of an external system under the control of the microcontroller. Voltage losses that may occur during the switched-capacitor charging are com- pensated to maintain the levels of the discrete voltages free of decay. Compensation is achieved by overcharging the capacitor by an amount substantially equivalent to the amount of voltage loss on the capacitor, using active feed- back obtained from monitoring the charge on the capacitor.
Inventors & Locations
James B. Nolan; Scott Ellison, both of Chandler; Brian Boles, Mesa; Rodney Drake, Phoenix; Russell E. Cooper
(Chandler, all of Ariz )
Patent #US5841996A
United States Patent 115
G08B21/00 • Battery Management & Monitoring Systems
H02J7/00 • Battery Chargers & Power Management ICs
Amicrocontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry such as a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corre- sponding digital counts indicative of signal level. The micro- controller also includes an I°C interface for supporting a bi-directional two wire bus and data tran: ion protocol that is useful for serially communicating with other periph- eral or microcontroller devices. By making use of the I°C interface, the microcontroller can be programmed while in the end application circuit. Such a feature allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the prod- uct. This allows the most recent firmware or a custom firmware to be programmed.
Inventors & Locations
James B. Nolan, Chandler; Brian Dellacroce
(Sedona, both of Ariz )
Patent #US5841866A
United States Patent 115
G07F7/00 • Vending & Automated Transaction Terminals
G07F7/08 • Credit Card & ID Processing Terminals
A method of operating a circuit such as an integrated circuit carried on a plastic card which includes the steps of accept- ing a challenge, and generating a first response to the challenge using a first algorithm which operates on at least the challenge and a secret key derived from information relating to the circuit. The challenge may be generated, and accepted, by the circuit, with a corresponding challenge being generated externally of the circuit. Alternatively, the challenge is generated externally of the circuit and is then accepted by the circuit. A token count may be stored in the circuit and the first response is generated if a decrement command is successfully carried out on the token count.
Inventors & Locations
Frederick Johannes Bruwer; Pieter Jacobus Pretorius; Theodor Johannes Dippenaar
(all of Verwoerdburg, South Africa )
Patent #US5835410A
United States Patent 115
G11C7/00 • Semiconductor Memory Chips
G11C7/06 • Memory Integrated Circuits
A self timed precharge sense amplifier for allowing high speed reading of a memory cell of a memory array. The self timed precharge sense amplifier uses a precharge device for generating an output voltage which is used to ramp up a voltage level of a column of the memory array where the memory cell is located. State control circuitry is coupled to the precharge device for activating and deactivating the precharge device. A sense amplifier is coupled to the pre- charge device and to the state control circuitry for monitor- ing the output voltage of the precharge device and for signalling the state control circuitry to deactivate the pre- charge device when the output voltage has reached a thresh- old voltage level set by the sense amplifier which is a minimum amount of voltage required to properly read the memory cell.
Inventors & Locations
Randy L. Yach, Phoenix; Richard L. Hull
(Chandler, both of Ariz )
Patent #US5812456A
United States Patent 115
G11C16/00 • EPROM and Flash Memory Chips
G11C16/02 • EEPROM and Flash Memory Devices
A technique for reading data from a selected memory element of an EPROM array having rows and columns with addressable memory elements which may be selectively accessed at respective intersections of the rows and columns. Each memory element includes a transistor having gate, source and drain electrodes, and after selection of a particu- lar memory element from which data is to be read by appropriately biasing the row and column associated with that memory clement, the source electrode thereof is selec- tively connected to ground by a switching element to allow current flow through the source-drain path of the memory element and enable the readout of data therefrom after the drain and gate voltages of the memory element have stabi- lized.
Inventors & Locations
Richard Hull, Chandler; Randy L. Yach
(Phoenix, both of Ariz )
Patent #US5805507A
United States Patent 115
G11C16/00 • EPROM & Flash Memory Devices
G11C16/02 • Embedded Non-Volatile Memory ICs
A technique is disclosed for reading a memory element of an EPROM array embedded in a microcontroller chip which has been scaled down from a previous design by virtue of reduced line widths of a process technology used for fabri- cating the chip. The microcontroller chip has a predeter- mined supply voltage, and the array comprises rows and columns of addressable memory elements which may be selectively accessed to read data content therefrom in a low voltage mode in which the supply voltage initially rises and ultimately reaches substantially its maximum voltage during a read cycle. A regulated reference voltage is used to exercise row and column control in the low voltage read mode by tracking the level of the supply voltage up to a certain preselected level below the maximum supply voltage, and by clamping the row and column control voltage at substantially the preselected level despite increases in the level of the supply voltage above the preselected level.
Inventors & Locations
Richard Hull, Chandler; Randy L. Yach
(Phoenix, both of Ariz )
Patent #US5774733A
United States Patent 115
H03M1/00 • Data Conversion Integrated Circuits
H03M1/12 • Data Conversion Integrated Circuits
Amicrocontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry including a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The slope A/D converter includes a digital-to-analog con- verter (DAC) for providing a programmable charging cur- rent to generate a voltage across a capacitor, a precision comparator having inputs for receiving a selected analog input and the capacitor voltage, a counter and a capture register. After a reset is performed, the capacitor is charged while the counter begins counting such that when the capacitor voltage exceeds the selected analog input voltage, the comparator switches logic states thereby causing the obtained count of the counter to be stored in the register. This stored count represents the time that it took for the capacitor to charge up and exceed the selected analog input voltage and corresponds to voltage measurement of the selected analog input.
Inventors & Locations
James B. Nolan, Chandler; Brian Dellacroce
(Sedona, both of Ariz )
Patent #US5764099A
United States Patent 1)
H02J9/00 • Power Management Integrated Circuits (PMICs)
H02J9/005 • Battery-Powered Electronic Encoding Devices & Remote Controls
According to the present invention, there is provided an integrated circuit useful in an electronic encoding device having a voltage source. a user interface and a transmitter. In one embodiment the integrated circuit includes a wake-up circuit which generates a signal responsive to an input received from the user interface; power switching logic which provides power from the voltage source to a non- regulated power bus and a voltage regulating circuit. the power switching logic being responsive to the signal from the wake-up circuit; a regulated power bus in communica- tion with the voltage regulating circuit; non-volatile memory in communication with the regulated power bus; encoder logic in communication with the regulated power bus. the encoder logic having output logic which provides a signal to the transmitter.
Inventors & Locations
Kent Hewitt
(Mesa. Ariz. [73])
Patent #US5760720A
United States Patent 9
G01R35/00 • Battery Management ICs
G01R35/005 • Battery Management ICs
Amicrocontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry such as a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corre- sponding digital counts indicative of signal level. In order to make the measurements of the selected analog inputs more precise, the microcontroller uses a unique calibration pro- cedure whereby selected parameters associated with the analog circuitry that are subject to variation are measured during test and corresponding calibration constants are cal- culated therefrom and stored in program memory. These stored calibration constants are subsequently used by the microprocessor in conjunction with the digital counts of the analog input signals for calculating a more precise measure- ment of the analog input signals.
Inventors & Locations
James B. Nolan; Hung Q. Nguyen. both of Chandler; Brian Dellacroce. Sedona
(all of Ariz)
Patent #US5742155A
United States Patent 1
G05F1/00 • Voltage References & Regulators
G05F1/10 • Voltage References & Regulators
A zero-current start-up circuit for a reference circuit which is initially unbiased and which has internal nodes that needs to be regulated to a predetermined voltage. When the start-up circuit is enabled, a switching transistor is turned on which enables the reference circuit to generate an internal reference current which regulates an output current to a predetermined value set by the reference circuit. The output current flows through a voltage drop device and when the voltage Jevel reaches a predetermined value, the start-up circuit is disabled eliminating the current path.
Inventors & Locations
David M. Susak, Phoenix; Joseph A. Thomsen
(Gilbert, both of Ariz )
Patent #US5703809A
United States Patent 14
G11C7/00 • Memory Integrated Circuits
G11C16/00 • EPROM and Flash Memory Chips
A method of high speed reading of data from an EPROM, in which a memory array is programmed based on device status at intersections of rows and columns of the array to store data therein as 0’s and 1’s, uses a capacitive over- charging and discharging technique to enable fast voltage stabilization without drawing significant current. A row containing the memory element to be read is quickly over- driven to overcharge an effective capacitance associated with the row to substantially the maximum level of the EPROM supply voltage which may exceed the programmed threshold voltage of the selected memory element. The effective capacitance is thereupon discharged to a predeter- mined voltage level below both the maximum level of the supply voltage and the programmed threshold. Then the status and data content of the selected memory element are read by first grounding an electrode of a source-drain path of a transistor comprising the memory element to cause current with substantially no DC component to flow through that path of the transistor. A sense amplifier in the source-drain path of the transistor is triggered to detect current flow therethrough as indicative of the data content of the memory element.
Inventors & Locations
Richard Hull, Chandler; Randy L. Yach
(Phoenix, both of Ariz )
Patent #US5694067A
United States Patent 1
H03L7/00 • Microcontrollers & SoCs
G06F15/00 • Microcontrollers & SoCs
The present invention relates to a microcontroller that may be configured to operate without the accompaniment of any external components. The microcontroller can function in a proper manner from the application of only power and signal lines with no external components required. The microcon- troller has integrated internal reset and oscillator circuitry into the microcontroller. The microcontroller has also inte- grated simple external components such as current limiting resistors and pull u and pull down resistor into the micro- controller in order to avoid application specific external
Inventors & Locations
Richard L. Hull, Chandler; Gregory C. Bingham, Gilbert; Scott R. Fink, Glendale; James Clark Rogers, Phoenix; Ryan Scott Ellison
(Chandler, all of Ariz )
Patent #US5686844A
United States Patent 119
H03K19/00 • Programmable Logic Devices & SoCs
H03K19/0175 • Semiconductor Interface Chips & SoCs
he present invention relates to a configurable IC device pin. he IC device pin may be a device clock input pin or a igital I/O pin in one embodiment of the present invention, ra reset pin or a digital I/O pin in another embodiment of le present invention. Both embodiments of the present vention use a memory device to store information to onfigure the IC device pin. Input/Output logic is also used | both embodiments in order to transfer data to and from the > device pin when the IC device pin is configured as a igital I/O pin.
Inventors & Locations
Richard L. Hull; Ryan Scott Ellison
(f both of Chandler, Ariz. ‘ )
Patent #US5619430A
United States Patent 11»)
G05D23/00 • Battery Management & Thermal Regulation ICs
G05D23/19 • Battery Management & Thermal Regulation ICs
A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry including a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The microcontroller further includes an on-chip temperature sensor, used in conjunction with the A/D converter, to monitor the temperature of the microcontroller. The tem- perature sensor generates and uses a differential voltage that is obtained across the base-emitter functions of two com- patible bipolar transistors having dissimilar emitter areas. This differential voltage is proportional to temperature and may be sampled by the A/D converter to obtain a digital count indicative of the temperature of the microcontroller,
Inventors & Locations
James B. Nolan; Russell E. Cooper, both of Chandler; Brian Dellacroce
(Sedona, all of Ariz )
Patent #US5604701A
United States Patent 119)
G11C7/00 • Semiconductor Memory Chips
G11C7/10 • Memory Controllers & Interface ICs
A sequential memory device having a read pipeline data structure for reading data from a bitline of a memory array of the device is disclosed. The read pipeline data structure includes at least one data path including a sense amp for sensing the logic level appearing on the bitline, a flip-flop for providing an output signal indicative of the data bits received on the bitline, and means for initializing the data path upon power up of the device such that the first data bit from the memory array is available for output from the device without the need and before the occurrence of a clock signal.
Inventors & Locations
Samuel E. Alexander, Phoenix; Kent D. Hewitt
(Gilbert, both of Ariz )
Patent #US5587866A
United States Patent 119)
H02H3/00 • Power Distribution & Protection Modules
H02H3/24 • Undervoltage Lockout (UVLO) & Reset ICs
A power-on reset circuit
Inventors & Locations
Randy L. Yach, Phoenix; Richard L. Hull
(Chandler, both of Ariz )
Patent #US5577235A
United States Patent 15
G06F15/00 • Microcontrollers & SoCs
G06F15/76 • Microcontrollers & SoCs
A microcontroller chip with a central processing unit (CPU) is adapted to control an external system with which the device is to be installed in circuit. The microcontroller chip includes an on-chip peripheral universal timing function module with a register for storing a value selected to signify a distinctive event in a waveform. A timer generates a series of values as a function of time as a measure of the value selected to signify the distinctive event. The register and the limer are coupled to a pin of the microcontroller chip on which said waveform is to be applicd. Equality between the values in the timer and the register signify the distinctive event as one of a capture and a compare of an event in the waveform, to generate an interrupt to the CPU. The register is selectively split into separate master and slave registers for automatic synchronization of the transfer of a value entered into the master register to the slave register with a repetitive boundary of the waveform, to provide selective pulse width modulation of the waveform.
Inventors & Locations
Sumit K. Mitra
(Tempe, Ariz )
Patent #US5504903A
United States Patent 19
G06F9/00 • Microcontrollers & SoCs
G06F9/06 • Microcontrollers & SoCs
A microcontroller fabricated on a semiconductor chip is adapted, when operating, to execute programs and instruc- tions and, in response, to generate control signals to selec- tively control external apparatus. A clock generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory has space avilable for storing a program to be executed by the micro- controller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the pro- gram memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.
Inventors & Locations
Chao-Wu Chen, Chandler, Ariz.; Kurt Rosenhagen; Greg Italiano, both of Hicksville, N.Y.; Sumit Mitra
(Tempe, Ariz )
Patent #US5488711A
United States Patent 15
G11C16/00 • EEPROM & Flash Memory Devices
G11C16/02 • Serial EEPROM Chips
A seria! EEPROM (eicctrically erasable programmable read only memory) device and method for reducing the time required to load data into the serial EEPROM device using a special write cache are disclosed. The EEPROM has an internal memory array for receiving a burst of data sent by a microcontroller, Data in the burst of data is initially loaded into an SRAM (static random access memory) write cache where it is stored sequentially and grouped in a plurality of pages, so that the bus and the microcontroller are freed to allow the microcontroller to perform other processing tasks at least until the EEPROM memory is written and the EEPROM is again accessible to the microcontroller, Writing of the internal memory array is accomplished sequentially with data from the pages of the cache loaded into rows of the internal memory array until the cache is depleted, the pages being sized so that an integral number of pages is stored in each row of the internal memory array.
Inventors & Locations
Kent D. Hewitt, Tempe; Samuel E. Alexander, Gilbert; Richard J. Fisher
(Phoenix, all of Ariz )
Patent #US5473758A
United States Patent 19
G11C16/00 • Erasable Programmable Read-Only Memory (EPROM) Chips
G11C16/02 • EEPROM & Flash Microcontrollers
A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The micro- controller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit pro- gramming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel. in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.
Inventors & Locations
Ray Allen, Mesa; Sumit Mitra, Tempe; Rodney Drake
(Mesa, all of Ariz )
Patent #US5469557A
United States Patent 19
G11C8/00 • Microcontrollers & SoCs
G11C8/20 • Secure Microcontrollers & Processors
A semiconductor microcontroller device is adapted to con- trol the operation of an external system. The device includes a CPU, program memory for storing instructions to be executed by the CPU to perform its control functions, and data memory for storing data for selective retrieval by the CPU. The contents of either memory are code protected by an EEPROM fuse, and are automatically erased if the code protect state of the EEPROM fuse is sought to be reset, and the EEPROM fuse is reset only after the erasure of the memory contents.
Inventors & Locations
Tom Salt, Chandler; Rodney Drake
(Mesa, both of Ariz )
Patent #US5454114A
United States Patent o5
G06F1/00 • Microcontrollers & SoCs
G06F1/24 • Microcontrollers & SoCs
A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The micro- controller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predeter- mined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution. In the disclosed embodiment, the reset condi- tion is maintained by a power-up timer and an oscillator start-up timer, each timer having a programmable timeout interval to end the reset condition only when the timeout intervals of both timers have expired.
Inventors & Locations
Randy L. Yach, Phoenix; Sumit Mitra
(Tempe, both of Ariz. 73] )
Patent #US5422807A
United States Patent ji)
H03M1/00 • Data Converters & Mixed-Signal Integrated Circuits
H03M1/06 • Mixed-Signal Microcontrollers
A semiconductor microcontroller includes the capabil- ity to perform analog to digital conversions of an analog signal representative of a variable parameter indicative of the need to exercise a control function. While the analog to digital conversions are being performed, the microcontroller processor can be powered down to eliminate noise arising from switching activities of the processor as a source of inaccuracy in the conversion process. At the end of the conversion, the analog to digital converter can either shut itself down or wake up the processor. The powering down is achieved by sim- ply disabling the clock input to the microcontroller so that the processor is still activated but incapable of undergoing switching functions.
Inventors & Locations
Sumit Mitra, Tempe; Russ Cooper, Chandler, both of Ariz.; Martin Burghardt
(Oberneuching, Germany )
Patent #US5371709A
United States Patent (1
G11C16/00 • Serial EEPROM Chips
G11C16/02 • Electrically Erasable Programmable Memory ICs
Power consumption of a serial EEPROM is reduced while simultaneously precluding data corruption during write operations. These results are achieved by operat- ing a brownout detector in the device to sense EE- PROM supply voltage below a predetermined level and thereupon to place the EEPROM in a reduced power mode, but only during an interval that a write sequence is taking place. Such an interval includes loading of data in a temporary storage cache and writing the loaded data into the EEPROM. At the same time that the low voltage level is detected during a write sequence, any load or write operation then in progress is aborted. The brownout detector is intentionally left disabled or in a sleep mode during any read mode or standby mode since there is no jeopardy of corrupting the EEPROM memory during those times.
Inventors & Locations
Richard J. Fisher, Phoenix; Samuel E. Alexander
(Gilbert, both of Ariz )
Patent #US5367484A
United States Patent 15)
G11C29/00 • Flash Memory Management Systems
G11C29/70 • Fault-Tolerant Memory Controllers
An erasable programmable memory device has a num- ber of data storage blocks. Each block has an endurance characteristic that at least roughly defines the number of times data may be erased from and written to the block before it wears out in that data cannot then be further erased from and written to the block. A redun- dant data storage block of memory capacity and endur- ance similar to that of each of the other data storage blocks is disposed in parallel with a selected one of the latter for which higher endurance is desired. This ena- bles identical data to be written simultaneously to the two blocks and thus considerably increases the endur- ance of the selected block by virtue of the fact that identical memory cells in both blocks must fail before the endurance of the selected block will be depleted. After the selected block has been designated for high endurance and placed in parallel with the redundant block, a fuse may be set to prevent alteration of that designation.
Inventors & Locations
Samuel E, Alexander, Gilbert; Stephen V. Drehobl; Richard J. Fisher, both of Phoenix; Leonard F, French, Chandler; Kent D, Hewitt
(Tempe, all of Ariz )
Patent #US5363334A
United States Patent 15
G11C16/00 • EPROM & EEPROM Memory Chips
G11C16/02 • EEPROM and Flash Memory ICs
An erasable programmable memory device has a num- ber of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereaf- ter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write pro- tection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by com- paring each write operation address with the addresses of the data storage cells encompassed within the pro- tected area, and if it is within that area, aborting the write operation.
Inventors & Locations
Samuel E. Alexander, Gilbert; Richard J. Fisher, Phoenix; Kent D. Hewitt
(Tempe, all of Ariz )
Patent #US5351216A
United States Patent 19
G05B19/00 • Microcontrollers & SoCs
G05B19/02 • Microcontrollers & SoCs
A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively exe- cuted by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be writ- ten to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is imple- mented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asyn- chronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.
Inventors & Locations
Tom Salt, Chandler; Rodney Drake, Mesa; Ray Allen
(Mesa, all of Ariz )
Patent #US5345413A
United States Patent
G11C7/00 • Non-Volatile Memory ICs
G11C7/24 • Secure Microcontrollers & Protected Memory ICs
The usability of an electrically erasable programmable semiconductor memory device is assured after shipment from the factory despite implementing the device with a user option to selectively configure the security, en- durance, organization, density or protocol of the mem- ory array of the device. The user selected configuration is made permanent and inaccessible for change by pro- gramming associated normally reversible configuration fuses which are rendered incapable of being repro- grammed (reversed) thereafter by the automatic and simultaneous programming of a lockout fuse. Final testing of the device at the factory is permitted by an override of the lockout fuse during testing of the opera- tion of the configuration fuses, and, when the testing is completed, returning, under program control, all fuses to a default condition in which the configuration fuses are limited to one-time programmability as a conse- quence of automatic simultaneous programming of the lockout fuse and configuration fuses at any time after shipment of the device from the factory.
Inventors & Locations
Richard J. Fisher, Phoenix; Samuel E, Alexander
(Gilbert, both of Ariz )
Patent #US5294928A
United States Patent 115)
H03M1/00 • Data Converters & Microcontrollers
H03M1/002 • Power-Managed Microcontrollers
A semiconductor microcontroller includes the capabil- ity to perform analog to digital conversions of an analog signal representative of a variable parameter indicative of the need to exercise a control function. While the analog to digital conversions are being performed, the microcontroller processor can be placed in a sleep mode which eliminates noise arising from switching activities of the processor as a source of inaccuracy in the conver- sion process. At the end of the conversion, the analog to digital converter can either shut itself down or wake up the processor. Alternatively, the converter may shut itself down in response to a different user selected con- trol signal.
Inventors & Locations
Russ Cooper, Chandler; Sumit Mitra
(Tempe, both of Ariz )
Patent #US5212780A
United States Patent 11
G06F5/00 • RAM Controllers & Memory Subsystems
G06F5/01 • RAM Controllers & Memory Subsystems
The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruc- tion results in externally generated row and column address signals which are decoded to cause a first mem- ory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder in- cludes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.
Inventors & Locations
Ajay J. Padgaonkar, Phoenix; Sumit K. Mitra
(Tempe, both of Ariz )
82 Patents Found