AI Patent Summary

Patent Document
#US5889829A
United States Patent 115
Abstract
A phase-locked loop (PLL) circuit is used to synchronize a local clock frequency with an edge of a reference clock frequency, employing a phase detector to compare the local clock frequency and the reference clock frequency to gen- erate a control signal indicative of the need to increase or to decrease the local clock frequency for phase locking thereof to the reference clock frequency. A voltage controlled oscil- lator (VCO) is responsive to a signal voltage derived from the control signal to vary the local clock frequency as necessary to achieve phase locking. A loop filter has a reference voltage threshold level which is pre- programmable to enable the loop filter to respond to the control signal by adjusting the signal voltage as a virtual step function toward the programmed reference voltage thresh- old level before application to the VCO, and then cycling up and down in a search for a stable control signal voltage to reduce the time necessary to achieve the desired phase locking.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC H03L7/00
Confidence: High
Official Definition
Automatic control of frequency or phase; Synchronisation
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Clock Generation & Synchronization
Product Category:
Phase-Locked Loop (PLL) Integrated Circuits
Plain-English Summary:
Systems and methods that automatically regulate or control the frequency or phase of an electronic signal to keep it synchronized with another signal.
Relation to Claims:
The patent discloses a phase-locked loop (PLL) circuit designed to synchronize a local clock frequency with a reference clock edge, falling squarely into general frequency and phase control.
CPC H03L7/06
Confidence: High
Official Definition
Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Clock Generation & Synchronization
Product Category:
Phase-Locked Loop (PLL) Integrated Circuits
Plain-English Summary:
Controlling signal frequency or phase by comparing a local oscillator's output against an external reference signal inside a feedback loop.
Relation to Claims:
The abstract explicitly details comparing a local clock frequency with a reference clock frequency using a phase detector to generate a control signal for phase locking.
CPC H03L7/08
Confidence: High
Official Definition
Details of the phase-locked loop
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Analog & Mixed-Signal Circuit Design
Product Category:
Phase-Locked Loop (PLL) Subcomponents
Plain-English Summary:
Specific structural or operational sub-components and circuit designs that make up a phase-locked loop system.
Relation to Claims:
The patent outlines specific circuit blocks including a phase detector, a voltage controlled oscillator (VCO), and a loop filter.
CPC H03L7/10
Confidence: High
Official Definition
Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Fast-Lock Phase-Locked Loops
Product Category:
High-Speed Clock Synthesizers
Plain-English Summary:
Circuit features in a phase-locked loop specifically engineered to help the system lock onto the target frequency faster or successfully start up from an unlocked state.
Relation to Claims:
The abstract emphasizes reducing the time necessary to achieve the desired phase locking by adjusting the signal voltage as a virtual step function.
CPC H03L7/12
Confidence: Medium
Official Definition
Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a scanning signal
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Fast-Lock Phase-Locked Loops
Product Category:
High-Speed Clock Synthesizers
Plain-English Summary:
Using a sweeping or scanning control signal to help a phase-locked loop rapidly find the correct operating frequency during startup.
Relation to Claims:
The patent describes the loop filter cycling up and down in a search for a stable control signal voltage, aligning with scanning or searching behavior to achieve initial synchronization.