AI Patent Summary

Patent Document
#US6029241A
United States Patent 115
Abstract
A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor archi- tecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode. An instruction register is coupled to the selection circuit for supplying a bank address values for an instruction to be executed in a direct long addressing mode and for supplying a register address within a bank for the instruction to be executed in a direct short addressing mode.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G06F12/00
Confidence: High
Official Definition
Accessing, addressing or allocating within memory systems or architectures
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Computer Architecture & Memory Systems
Product Category:
Microprocessors & Memory Controllers
Plain-English Summary:
Techniques and hardware for accessing, locating, and managing spaces inside computer memory systems.
Relation to Claims:
The patent outlines a processor architecture featuring a data memory divided into banks and a selection circuit to handle multiple addressing modes, which directly corresponds to how memory systems are accessed and addressed.
CPC G06F12/02
Confidence: High
Official Definition
Addressing or allocation; Relocation
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Memory Addressing & Management
Product Category:
Microprocessors & Memory Controllers
Plain-English Summary:
Methods and circuits for determining where data is stored in memory, assigning memory blocks, or shifting data locations.
Relation to Claims:
The abstract specifically discusses bank address generation, bank select registers, and supplying register addresses for different addressing modes (direct short and direct long), aligning closely with memory addressing and allocation.
CPC G06F9/00
Confidence: High
Official Definition
Arrangements for program control, e.g. control units
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Control & Execution Units
Product Category:
Central Processing Units & SoCs
Plain-English Summary:
General architectural arrangements for controlling the execution of programs within a processor, including control units.
Relation to Claims:
The patent details a processor architecture scheme featuring a CPU that executes an instruction set, which falls under program control and control unit arrangements.
CPC G06F9/06
Confidence: High
Official Definition
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Embedded Systems & Stored-Program Architecture
Product Category:
Microcontrollers & Processors
Plain-English Summary:
Architecture for controlling computer programs using internal memory or storage to hold instructions and data.
Relation to Claims:
The invention describes a CPU executing an instruction set using a data memory divided into banks and an instruction register supplying address values for instructions, characteristic of stored-program processing equipment.
CPC G06F9/30
Confidence: High
Official Definition
Arrangements for executing machine instructions, e.g. instruction decode
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Instruction Set Architecture (ISA) & Execution Logic
Product Category:
CPU Execution Units & Microcontrollers
Plain-English Summary:
Hardware and logic designed to process, decode, and execute specific machine-level instructions given to a processor.
Relation to Claims:
The patent details instruction-driven mechanisms including an instruction register supplying bank and register addresses for direct short and long addressing modes during instruction execution.