AI Patent Summary

Patent Document
#US5874863A
United States Patent 115
Abstract
A phase-locked loop (PLL) circuit has a phase comparator for comparing the phases of a local clock frequency and a reference frequency to generate a control signal indicative of a direction of adjustment of the local clock frequency for reducing the phase difference between the two frequencies. A voltage controlled oscillator (VCO) of the PLL responds to application of a control voltage thereto to generate an oscillation signal frequency from which the local clock frequency is derived. A loop filter responds to the control signal from the phase comparator to develop a control voltage for application to the VCO to adjust the local clock frequency in the direction indicated by the control signal to reduce the relative phase difference. The loop filter has a start-up cil reference frequency after a predetermined number of cycles following commencement of operation or reset of the PLL circuit as being indicative of stabilization of the reference frequency, and is responsive to detection of such selected edge for promptly producing a linear boost of the control voltage from an initial level of substantially zero volts to a predetermined pull-up level exceeding the level of control voltage required to achieve phase locking. This reduces the time interval required to achieve phase locking, measured from the selected cycle edge. The loop filter is also respon- sive to the control voltage reaching the pull-up level to incrementally reduce the control voltage to the level required to achieve phase locking.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC H03L7/00
Confidence: High
Official Definition
Automatic control of frequency or phase; Synchronisation
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Analog & Mixed-Signal Circuitry
Product Category:
Clock Generation & Timing ICs
Plain-English Summary:
Systems and methods that automatically regulate electronic frequency or phase, keeping signals properly synchronized.
Relation to Claims:
The patent discloses a phase-locked loop (PLL) circuit designed for automatic frequency and phase control to align a local clock with a reference frequency.
CPC H03L7/06
Confidence: High
Official Definition
Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Phase-Locked Loop (PLL) Architecture
Product Category:
Frequency Synthesizers & Clock Generators
Plain-English Summary:
Controlling frequency or phase by comparing an internal signal against an external reference signal inside a locked loop.
Relation to Claims:
The patent utilizes a phase comparator to compare a local clock frequency against a reference frequency, forming the core feedback loop.
CPC H03L7/08
Confidence: High
Official Definition
Details of the phase-locked loop
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Analog & Mixed-Signal Circuitry
Product Category:
Semiconductor Timing Components
Plain-English Summary:
Specific internal component designs and sub-circuits that make up a phase-locked loop, such as loop filters and voltage-controlled oscillators.
Relation to Claims:
The patent details specific components of the PLL, including a voltage-controlled oscillator (VCO), a phase comparator, and a loop filter working together.
CPC H03L7/10
Confidence: High
Official Definition
Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Fast-Lock PLL Design
Product Category:
High-Speed Communication & Timing ICs
Plain-English Summary:
Mechanisms within a phase-locked loop designed to help the circuit lock onto a target frequency quickly when it first starts up.
Relation to Claims:
The abstract explicitly highlights a start-up circuit that produces a linear boost of control voltage to reduce the time interval required to achieve phase locking.
CPC H03L7/12
Confidence: Medium
Official Definition
Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a scanning signal
ELECTRICITY > ELECTRONIC CIRCUITRY > AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
AI Technology & Product Mapping
Technology Domain:
Fast-Lock PLL Design
Product Category:
Clock Synthesis & Management Chips
Plain-English Summary:
Methods to achieve initial synchronization in a phase-locked loop by sweeping or scanning control voltages or frequencies during start-up.
Relation to Claims:
The loop filter responds to a selected edge to promptly produce a linear boost or voltage adjustment to facilitate rapid initial acquisition of the locked state.