AI Patent Summary

Patent Document
#US5991196A
United States Patent 115
Abstract
An improved reprogrammable memory device permits defi- nition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C16/00
Confidence: High
Official Definition
Erasable programmable read-only memories
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
Flash Memory Devices
Plain-English Summary:
Memory devices that can retain data without power, be erased, and be reprogrammed with new data.
Relation to Claims:
The patent relates generally to an improved reprogrammable memory device capable of erasing and reprogramming specific variable-sized pages of memory cells.
CPC G11C8/00
Confidence: High
Official Definition
Arrangements for selecting an address in a digital store
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Addressing & Control Logic
Product Category:
Memory Controllers & SoCs
Plain-English Summary:
Circuitry and methods used to locate and access specific storage locations or memory cells within a digital memory chip.
Relation to Claims:
The disclosure describes address decode logic coupled to the memory cell array for accessing specific rows and columns.
CPC G11C8/12
Confidence: High
Official Definition
Group selection circuits, e.g. for memory block selection, chip selection, array selection
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Addressing & Control Logic
Product Category:
Memory Subsystems
Plain-English Summary:
Circuits that select specific blocks, chips, or groups of memory cells within a larger memory array.
Relation to Claims:
The abstract specifies block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.
CPC G11C16/02
Confidence: High
Official Definition
Erasable programmable read-only memories electrically programmable
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Flash Memory Architecture
Product Category:
EEPROM and Flash Memory Chips
Plain-English Summary:
Flash or EEPROM memory devices that are programmed and erased using electrical signals rather than ultraviolet light.
Relation to Claims:
The patent outlines an array of memory cells arranged in rows and columns that can be selectively erased and reprogrammed electrically.
CPC G11C16/06
Confidence: High
Official Definition
Auxiliary circuits, e.g. for writing into memory
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Peripheral Circuitry
Product Category:
Memory Integrated Circuits
Plain-English Summary:
Support circuitry required to operate memory arrays, such as voltage amplifiers, column selectors, and control signal generators.
Relation to Claims:
The invention explicitly incorporates amplifier logic, column select logic, and control signals coupled to the amplifier logic for accessing the memory array.