AI Patent Summary

Patent Document
#US5488711A
United States Patent 15
Abstract
A seria! EEPROM (eicctrically erasable programmable read only memory) device and method for reducing the time required to load data into the serial EEPROM device using a special write cache are disclosed. The EEPROM has an internal memory array for receiving a burst of data sent by a microcontroller, Data in the burst of data is initially loaded into an SRAM (static random access memory) write cache where it is stored sequentially and grouped in a plurality of pages, so that the bus and the microcontroller are freed to allow the microcontroller to perform other processing tasks at least until the EEPROM memory is written and the EEPROM is again accessible to the microcontroller, Writing of the internal memory array is accomplished sequentially with data from the pages of the cache loaded into rows of the internal memory array until the cache is depleted, the pages being sized so that an integral number of pages is stored in each row of the internal memory array.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C16/00
Confidence: High
Official Definition
Erasable programmable read-only memories
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
EEPROM & Flash Memory Devices
Plain-English Summary:
Memory devices that can retain data without power and can be erased and reprogrammed.
Relation to Claims:
The patent directly relates to an EEPROM device, aligning with the foundational classification for erasable programmable read-only memories.
CPC G11C16/02
Confidence: High
Official Definition
Erasable programmable read-only memories electrically programmable
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Electrically Erasable Memory
Product Category:
Serial EEPROM Chips
Plain-English Summary:
Memory chips that can be programmed and erased using electrical signals rather than ultraviolet light.
Relation to Claims:
The invention specifically describes a serial EEPROM device that is electrically erasable and programmable.
CPC G11C16/06
Confidence: High
Official Definition
Auxiliary circuits, e.g. for writing into memory
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Peripheral Circuitry
Product Category:
EEPROM Control Logic & Caches
Plain-English Summary:
Support circuitry integrated into memory devices, such as circuits specifically used to write or store data into the memory array.
Relation to Claims:
The patent utilizes an SRAM write cache and internal logic to handle data bursts, falling squarely under auxiliary writing circuits.
CPC G11C16/10
Confidence: High
Official Definition
Programming or data input circuits
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Data Input and Programming
Product Category:
Memory Controllers & Interface Logic
Plain-English Summary:
Circuits responsible for receiving data inputs and managing the programming sequence of the memory.
Relation to Claims:
The abstract details a mechanism for loading a burst of data into a write cache to streamline data input from a microcontroller.
CPC G11C16/102
Confidence: Medium
Official Definition
External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
In-Circuit Programming Interfaces
Product Category:
Microcontroller-Connected Memory Subsystems
Plain-English Summary:
Circuits or interfaces that allow memory devices to be programmed while integrated into a larger system, or via external programming equipment.
Relation to Claims:
The invention deals with data sent by an external microcontroller communicating with the EEPROM over a bus, relating to in-system data transfer and programming efficiency.