AI Patent Summary

Patent Document
#US6937084B2
United States Patent
Abstract
A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switch- ing devices that are connected to PWM hardware included in a processor. Complementary PWM output signals have dual deadtime delay in which the delay between the inacti- vation of the first signal and the activation of the second signal may be different than the delay between the inacti- vation of the second signal and the activation of the first signal. This provides an improved capability to deal with non-symmetric switching characteristics of the external switching devices, and the circuitry to which they are connected. The dual deadtime pulse width modulation gen- erator for a processor includes deadtime generation circuitry operable to generate a first pulse width modulated signal and a second pulse width modulated signal complementary to the first pulse width modulated signal, wherein there is a first delay between inactivation of the first pulse width modu- lated signal and activation of the second pulse width modu- lated signal, a second delay between inactivation of the second pulse width modulated signal and activation of the first pulse width modulated signal, and the first and second delays are not equal. The first delay and the second delay may be independently settable. 16 Claims, 6 Drawing Sheets
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC H02M1/00
Confidence: High
Official Definition
Details of apparatus for conversion
ELECTRICITY > GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER > APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
AI Technology & Product Mapping
Technology Domain:
Power Electronics & Conversion
Product Category:
Digital Power Controllers & Inverter Modules
Plain-English Summary:
General operational details, control circuitry, and auxiliary hardware used within power conversion systems and power supplies.
Relation to Claims:
Relates to the application context where the processor's PWM module is utilized to drive power converter switching stages such as half-bridge or H-bridge topologies.
CPC H02M1/38
Confidence: High
Official Definition
Means for preventing simultaneous conduction of switches
ELECTRICITY > GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER > APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
AI Technology & Product Mapping
Technology Domain:
Power Management & Gate Driver Control
Product Category:
Motor Drive Controllers & Half-Bridge Gate Drivers
Plain-English Summary:
Protection circuits and timing mechanisms configured to prevent 'shoot-through' or cross-conduction (simultaneous turn-on) in complementary power switches.
Relation to Claims:
Directly matches the core invention, which implements independently settable dual deadtime delays to prevent bridge switch overlap caused by asymmetrical switching speeds of external power switches.
CPC H03K5/00
Confidence: High
Official Definition
Manipulating of pulses not covered by one of the other main groups of this subclass
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Pulse Generation & Signal Conditioning
Product Category:
Pulse Width Modulation (PWM) Peripheral ICs
Plain-English Summary:
Circuit arrangements designed to shape, modify, delay, or process electronic pulse signals.
Relation to Claims:
Covers the internal digital logic of the processor that modulates pulse widths and injects asymmetric delay intervals into the generated pulse streams.
CPC H03K5/15
Confidence: High
Official Definition
Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Embedded Systems & Digital Timing Logic
Product Category:
Microcontrollers & Digital Signal Processors (DSPs)
Plain-English Summary:
Timing and logic hardware that distributes pulse signals across multiple output pins with specific time delays or phase offsets.
Relation to Claims:
Applies to the processor subsystem outputting multiple timed PWM waveforms to separate control pins with distinct, independently adjustable delays.
CPC H03K5/151
Confidence: High
Official Definition
Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Digital Logic & Processor Peripherals
Product Category:
Microcontrollers & SoCs with Advanced PWM Modules
Plain-English Summary:
Pulse-generating circuits providing pairs of complementary (mutually inverted) digital signals with programmable non-overlapping delays.
Relation to Claims:
Specifically covers the disclosed architecture producing a first PWM signal and a complementary second PWM signal with non-equal, independently configured deadtime delays between respective transitions.