AI Patent Summary

Patent Document
#US5363334A
United States Patent 15
Abstract
An erasable programmable memory device has a num- ber of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereaf- ter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write pro- tection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by com- paring each write operation address with the addresses of the data storage cells encompassed within the pro- tected area, and if it is within that area, aborting the write operation.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C16/00
Confidence: High
Official Definition
Erasable programmable read-only memories
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
EPROM & EEPROM Memory Chips
Plain-English Summary:
Memory devices that can be erased and reprogrammed multiple times, typically utilizing non-volatile storage technologies.
Relation to Claims:
The patent relates generally to erasable programmable memory devices containing contiguous data storage cells.
CPC G11C16/02
Confidence: High
Official Definition
Erasable programmable read-only memories electrically programmable
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Electrically Erasable Programmable Memory
Product Category:
EEPROM and Flash Memory ICs
Plain-English Summary:
Memory chips that can be programmed and erased using electrical signals rather than ultraviolet light or other external physical means.
Relation to Claims:
The disclosure describes a memory device undergoing write operations that can be controlled and selectively write-protected electronically.
CPC G11C16/06
Confidence: High
Official Definition
Auxiliary circuits, e.g. for writing into memory
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Peripheral Circuitry
Product Category:
Memory Controller Logic
Plain-English Summary:
Supporting circuitry on a memory chip used to manage internal operations such as writing data, voltage regulation, or address decoding.
Relation to Claims:
The invention utilizes address comparison logic and write-aborted mechanisms to execute the write protection feature.
CPC G11C16/22
Confidence: High
Official Definition
Safety or protection circuits preventing unauthorised or accidental access to memory cells
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Hardware Security & Memory Protection
Product Category:
Secure Non-Volatile Memory
Plain-English Summary:
Security and safety mechanisms built into memory hardware to prevent data from being accidentally overwritten, erased, or accessed without authorization.
Relation to Claims:
This is the core of the invention: storing a starting address and a total number of cells to make specific data permanent by aborting unauthorized write operations.
CPC G06F12/00
Confidence: Medium
Official Definition
Accessing, addressing or allocating within memory systems or architectures
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Memory Addressing & Management
Product Category:
Memory Management Units (MMU)
Plain-English Summary:
Methods and hardware systems used by a computer processor or controller to read, write, locate, and manage data storage locations in memory.
Relation to Claims:
The patent deals with storing specific cell addresses and comparing target write addresses against protected address ranges to manage data allocation safety.