AI Patent Summary

Patent Document
#US6349058B1
a2) United States Patent
Abstract
An electronic circuit includes a non-volatile memory that has several memory cells. The output of the non-volatile memory is connected to the inputs of several latches. Each latch has an output adapted to be read independently. A refresh circuit is connected to address lines of the non- volatile memory and to the write pins of cach of the latches. The data contained in the memory cells of the non-volatile memory is represented by the data contained in the latches. 22 Claims, 3 Drawing Sheets
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C7/00
Confidence: High
Official Definition
Arrangements for writing information into, or reading information out from, a digital store
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
Memory Integrated Circuits
Plain-English Summary:
Circuits and systems designed for transferring data into or out of digital memory storage devices.
Relation to Claims:
The patent disclosure describes an electronic circuit involving a non-volatile memory connected to latches via refresh and address lines, directly mapping to data transfer and storage operations covered by this classification.
CPC G11C7/10
Confidence: High
Official Definition
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Interfaces & Control Circuits
Product Category:
Memory Controller Components
Plain-English Summary:
Hardware mechanisms and interface circuits that manage the flow of data entering or leaving a memory device.
Relation to Claims:
The patent outlines output connections from a non-volatile memory into several latches, establishing an internal data interface arrangement.
CPC G11C7/1078
Confidence: Medium
Official Definition
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Digital Storage Input Regulators
Product Category:
Memory Write Buffer Circuits
Plain-English Summary:
Circuits that receive and condition data signals before they are written into a storage element, such as registers or write amplifiers.
Relation to Claims:
The invention uses a refresh circuit connected to write pins of latches and address lines to write data derived from memory cells, aligning with data input and writing circuitry.
CPC G11C7/1093
Confidence: Medium
Official Definition
Input synchronization
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Synchronous Memory Control
Product Category:
Timing and Control Logic
Plain-English Summary:
Circuitry used to synchronize incoming data or control signals with internal clock signals or timing references within a memory device.
Relation to Claims:
The presence of refresh circuits communicating with address lines and write pins implies the need for coordinated timing and synchronization of data transfers between the memory cells and latches.
CPC G11C11/00
Confidence: High
Official Definition
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Cells
Product Category:
Semiconductor Memory Chips
Plain-English Summary:
Digital memory systems defined by the specific types of electrical or magnetic components used to hold data values.
Relation to Claims:
The abstract explicitly relies on a non-volatile memory comprising a plurality of memory cells whose data is represented by connected latches, falling squarely into specific digital storage elements.