AI Patent Summary

Patent Document
#US6204708B1
United States Patent
Abstract
An improved master-slave flip-flop that is characterized by anovel clock generator. The improved flip-flop preserves the true mast ave relationship by ensuring a two ste ing process is executed by non-overlapping cl clock generator features an inverter in combin current limiter. The current limiter has the effect of shifting the trip point of the inverter such that non-overlapping clocks may be derived from a single master clock signal or a master clock signal and its complement. 18 Claims, 9 Drawing Sheets s” I -102 40 CLK SLAVE Q LATCH -103
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC H03K3/00
Confidence: High
Official Definition
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Digital Logic & Timing Circuits
Product Category:
Integrated Circuits & Digital Logic
Plain-English Summary:
Electronic circuits used to create specific electrical pulses or maintain stable states, which form the foundational building blocks for digital logic and timing.
Relation to Claims:
The patent discloses a master-slave flip-flop and a novel clock generator, which directly fall under pulse generation and bistable circuit architectures.
CPC H03K3/02
Confidence: High
Official Definition
Generators characterised by the type of circuit or by the means used for producing pulses
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Clock Generation & Pulse Circuitry
Product Category:
Clock Generators & Timing ICs
Plain-English Summary:
Circuits specifically designed to generate electrical pulses based on the particular circuit arrangement or components utilized.
Relation to Claims:
The invention relies heavily on a novel clock generator utilizing an inverter and current limiter to derive non-overlapping clocks.
CPC H03K3/353
Confidence: High
Official Definition
Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
MOSFET Digital Circuit Design
Product Category:
Semiconductor Devices & Logic ICs
Plain-English Summary:
Pulse or signal generators built using field-effect transistors (FETs) that incorporate feedback loops to create switching actions.
Relation to Claims:
Flip-flops and clock generators are fundamentally implemented using transistor-level designs with active field-effect elements.
CPC H03K3/356
Confidence: High
Official Definition
Bistable circuits
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Sequential Logic & Memory Elements
Product Category:
Flip-Flops & Latches
Plain-English Summary:
Circuits that have two stable states, commonly known as flip-flops or latches, used to store binary data (1s and 0s).
Relation to Claims:
The patent specifically targets an improved master-slave flip-flop, which is a classic bistable circuit architecture.
CPC H03K3/356104
Confidence: High
Official Definition
Bistable circuits using complementary field-effect transistors
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
CMOS Sequential Logic Design
Product Category:
CMOS Microelectronics & ASICs
Plain-English Summary:
Flip-flops and storage elements built using complementary metal-oxide-semiconductor (CMOS) technology, pairing NMOS and PMOS transistors.
Relation to Claims:
The master-slave flip-flop and associated clock generator using inverters and current limiters are standard implementations within CMOS digital integrated circuit design.