AI Patent Summary

Patent Document
#US6098160A
United States Patent 115
Abstract
A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode, An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G06F12/00
Confidence: High
Official Definition
Accessing, addressing or allocating within memory systems or architectures
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Memory Architecture & Addressing Systems
Product Category:
Processor Core Subsystems
Plain-English Summary:
Methods and hardware circuits used to access, locate, and assign memory spaces within computer storage systems.
Relation to Claims:
The patent relies heavily on memory addressing fundamentals, describing a specialized data pointer and hardware logic to access memory using indirect addressing modes.
CPC G06F12/02
Confidence: High
Official Definition
Addressing or allocation; Relocation
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Memory Management & Addressing
Product Category:
Microcontroller Memory Units
Plain-English Summary:
Techniques for determining where data is stored in memory, assigning memory blocks, or shifting data addresses.
Relation to Claims:
The disclosure specifically handles memory addressing modifications like auto pre-incrementing and offset combination, which directly map to address generation and allocation sub-functions.
CPC G06F9/00
Confidence: High
Official Definition
Arrangements for program control, e.g. control units
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Architecture & Control Units
Product Category:
Central Processing Units (CPUs)
Plain-English Summary:
General architectural setups that govern how a processor directs the execution of software programs and coordinates internal operations.
Relation to Claims:
The patent outlines a processor architecture scheme that allows for encoding multiple indirect addressing modes within single execution cycles.
CPC G06F9/06
Confidence: Medium
Official Definition
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Embedded Systems & Microcontrollers
Product Category:
Microcontrollers & SoCs
Plain-English Summary:
Computer designs that execute instructions from an internal memory store, forming the basis of stored-program computers.
Relation to Claims:
Relates to the processor architecture scheme that interprets and processes stored machine instructions requiring indirect operand fetching.
CPC G06F9/30
Confidence: High
Official Definition
Arrangements for executing machine instructions, e.g. instruction decode
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Instruction Execution & Datapath Design
Product Category:
Processor Datapath IP
Plain-English Summary:
The hardware mechanisms and logic circuits used by a processor to decode and carry out individual machine-level instructions.
Relation to Claims:
The patent details single-cycle execution of indirect addressing modes, combining data pointer registers, incrementers, adders, and multiplexers directly within the execution datapath.