AI Patent Summary

Patent Document
#US6057705A
United States Patent 115
Abstract
The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of addr or as alternate I/O pins. The object of the invention i provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programming logic, configura- tion logic, selection logic and a set of pins that may be configured as per the programmer’s requirements. The invention is to exist on a single, monolithic semiconductor device,
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC H03K19/00
Confidence: High
Official Definition
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Digital Logic & Semiconductor Circuits
Product Category:
Programmable Logic Devices & Microcontrollers
Plain-English Summary:
Basic electronic circuits that perform logical operations with multiple inputs and a single output, serving as the building blocks for digital processing.
Relation to Claims:
The patent discloses configuration and selection logic on a semiconductor device to dynamically route and define pin functions, aligning with foundational digital logic circuit operations.
CPC H03K19/0175
Confidence: High
Official Definition
Coupling arrangements; Interface arrangements
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Input/Output Interface Circuitry
Product Category:
Semiconductor Interface ICs
Plain-English Summary:
Circuit arrangements for connecting different logic families or signal interfaces together to communicate effectively.
Relation to Claims:
Relates directly to the programming ports, configuration logic, and multiplexing structures used to route alternate I/O or address signals to external pins.
CPC G06F1/00
Confidence: Medium
Official Definition
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Computer Hardware Architecture
Product Category:
General Computing Components
Plain-English Summary:
General architectural details and supporting hardware arrangements for computers not classified elsewhere.
Relation to Claims:
Applies generally to the monolithic semiconductor device architecture and bus sizing features described in the invention.
CPC G06F1/22
Confidence: High
Official Definition
Means for limiting or controlling the pin/gate ratio
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Integrated Circuit Design & Architecture
Product Category:
Microcontrollers & Programmable ICs
Plain-English Summary:
Hardware mechanisms designed to manage or optimize the ratio between external connection pins and internal logic gates on an integrated circuit.
Relation to Claims:
Directly maps to the core invention: allowing programmers to customize address bus size and designate pins as address or alternate I/O to optimize pin utilization on a monolithic semiconductor device.
CPC H03K19/02
Confidence: Medium
Official Definition
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
ELECTRICITY > ELECTRONIC CIRCUITRY > PULSE TECHNIQUE
AI Technology & Product Mapping
Technology Domain:
Semiconductor Device Physics & Circuit Design
Product Category:
Custom Logic ICs
Plain-English Summary:
Logic circuits constructed using specific types of electronic components or fabrication technologies.
Relation to Claims:
Covers the specific configuration logic and selection logic implemented on the monolithic semiconductor device.