AI Patent Summary

Patent Document
#US12346722B2
SYSTEMS AND METHODS FOR MANAGING INTERRUPT PRIORITY LEVELS
Abstract
A system includes non-transitory computer readable memory and a processor. The non-transitory computer read- able memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. ‘The processor to update the current processor interrupt priority level based on respective inter- rupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user- definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code. 20 Claims, 7 Drawing Sheets fe. 00 / ¥ RSOCESSOR IPL DISICTL IPL NSTRUCTIONS ‘OCESSOR IPL
AI Analysis & Synthesis
Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G06F13/00
Confidence: High
Official Definition
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Architecture and Interrupt Management
Product Category:
Microprocessors and Microcontrollers
Plain-English Summary:
The management and routing of data, control signals, and communication pathways between a computer's central processing unit, memory modules, and peripheral input/output devices.
Relation to Claims:
The patent claims detail mechanisms for managing interrupt priority levels via specific processor instructions and control registers, directly addressing how control signals and execution priorities are handled within the central processing unit and its interface with memory.
CPC G06F13/14
Confidence: High
Official Definition
Handling requests for interconnection or transfer
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Interrupt Management and Control Systems
Product Category:
Central Processing Units (CPUs) and Microcontrollers
Plain-English Summary:
Managing how different parts of a computer system or processor communicate, share data, and handle competing signals or requests.
Relation to Claims:
The patent claims detail systems and methods for handling processor interrupts and priority levels using specific registers and instructions (DISICTL), which falls under managing internal processor communication requests and priority handling.
CPC G06F13/20
Confidence: Medium
Official Definition
Handling requests for interconnection or transfer for access to input/output bus
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Interrupt and Bus Management Systems
Product Category:
Microprocessors and System-on-Chip (SoC) Integrated Circuits
Plain-English Summary:
Managing data transfers, communication requests, and interconnect access between internal computer components or input/output subsystems.
Relation to Claims:
The patent claims relate to managing interrupt priority levels and control instructions within a processor system, which coordinates internal resource access and exception handling, falling under broader computer architecture and input/output control mechanisms.
CPC G06F13/24
Confidence: High
Official Definition
Handling requests for interconnection or transfer for access to input/output bus using interrupt
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Interrupt and Exception Management
Product Category:
Microprocessors and Central Processing Units (CPUs)
Plain-English Summary:
Managing how computer processors handle hardware and software interrupts, specifically by controlling and prioritizing interrupt request levels to determine which tasks or exceptions take precedence during execution.
Relation to Claims:
The patent claims detail a system and processor architecture that maintain and compare multiple interrupt priority levels—specifically a current processor interrupt priority level and a user-definable disable interrupt control (DISICTL) priority level—directly implementing interrupt-based request handling mechanisms covered by the classification.
CPC G06F13/26
Confidence: High
Official Definition
Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Interrupt Management and Priority Control
Product Category:
Microprocessors and Microcontrollers
Plain-English Summary:
Managing how a computer system processes multiple hardware or software interruption signals based on their assigned priority levels to ensure critical tasks are handled first.
Relation to Claims:
The claims recite a processor and memory maintaining both a current processor interrupt priority level and a user-definable disable interrupt control (DISICTL) priority level, utilizing specialized instructions to update and apply the highest priority level during code execution, directly aligning with priority-controlled interrupt handling for bus access and internal operations.